1. Field of the Invention
The invention relates to a test structure and methods for verifying of isolation trench-etchings (trench etchings) in SOI wafers.
2. Description of Background and Other Information
For integrating logic elements at a low voltage level and high voltage power elements into the same silicon circuit it is necessary to insulate die regions having significantly differing potentials from each other. One option is the dielectric insulation using etched re-filled trenches (trench isolation). To this end a vertically acting insulation between the device and the substrate is realized by means of a buried (horizontal) insulating layer (typically comprised of silicon dioxide, while generally other insulating layers may be used). A laterally acting insulation is obtained by etching a trench to the buried insulating layer and subsequently re-filling the deep trench with insulating layers or with a single insulating layer (isolation trench).
Alternatively, only a portion of the etched trench may be filled with the insulating material. The remaining portion is filled with a conductive fill layer comprising, for instance, polysilicon. By a subsequent planarization, a so-called planarization step, for instance, an appropriate etch process or a chemical mechanical polishing (CMP) process, a planarization of the surface is accomplished, in this respect refer to the representation in FIG. 3 (prior art).
In known techniques various problems may arise with respect to the depth. In order to achieve electric insulation in the lateral direction, that is, from one insulated island to a adjacent insulated island, it has to be guaranteed that the isolation trench extends to the buried oxide. A typical conventional technique is hereby pushed to its physical limits. An endpoint detection based on the etch composition of the etch plasma (oxygen ions are present within the etch plasma when the buried oxide layer is reached) fails when the fraction of the area etched is too small.
Optical techniques are becoming increasingly difficult, when the aspect ratio, i.e., the ratio of width and depth, is too small, that is, for narrow deep trenches.
On the other hand, etching too long causes, due to back scattering of etch ions, an etch attack at the lower sidewalls of the etched trenches and should be avoided if possible.
Additionally, in view of a desirably high tool throughput during the manufacturing of SOI wafers including logic devices and power devices the etch time may not be extensively long.